1. Field of the Invention
The present invention relates to serial data communication networks and, in particular, to a clock and data recovery method and system for use in serial data communication networks allowing for fast bit lock acquisition and small data tracking errors.
2. Discussion of Related Art
Modern high-speed serial transceivers have received wide application in cross-chip and serial data communication networks. In contrast to their parallel counterparts, high-speed serial transceivers have the capability of extracting a clock signal encoded within a received data stream, allowing for network synchronization over a single data channel. This capability has subsequently eliminated the requirement of sending data and synchronization clock signals over multiple channels. In addition, several parallel data channels may be multiplexed and transmitted through a single serial data channel, increasing data transmission rates. These methods eliminate the stringent requirements on skew control between clock and data signals present in parallel data communication networks, and greatly simplify overall system design.
Designing reliable clock and data recovery (“CDR”) methods and systems, having the capability of extracting clock and data information contained within a transmitted serial data stream, proves crucial in the implementation of high-speed serial transceiver systems. A CDR system implemented in a high-speed serial transceiver may have multiple operating modes that depend on the state of an incoming input data stream. For example, during serial data link initialization before payload data is transmitted, data received by the serial transceiver may contain a CDR training data stream pattern. The training data stream may contain a synchronization clock signal embedded within rich data transitions in the data stream. By aligning an internal sampling clock to the embedded clock signal, the internal clock of the serial transceiver can be synchronized with the embedded clock signal. This process is called bit lock acquisition. Once bit lock is achieved, the serial transceiver may begin payload data transmission. Accordingly, due to inherent data transfer latencies during bit lock acquisition, reducing the time needed to achieve bit lock is a primary consideration in CDR system design.
During the transmission of payload data, the serial receiver must track minor phase changes in the incoming data. These minor phase changes are caused by a number of factors including system clock jitter and lane-to-lane interference. When left untracked by the CDR system, input data jitter can cause eye closure at sampling points and result in the overall degradation of system performance due to an increased bit error rate (“BER”). FIG. 1 illustrates the relationship between eye closure and BER graphically in graph 100. Two ideal digital pulses pdf(x) 104 without data jitter are shown centered one unit interval 110 apart. As illustrated in FIG. 1, one unit interval 110 represents the temporal spacing between adjacent bit intervals. A function illustrating the distribution of digital pulses with data jitter Cdf(x) 102 is also shown. The relationship between the distribution function Cdf(x) 102 and an ideal data pulse 104 is described by the relationship Cdf(0.1)=25, wherein as illustrated, 25% of pulse zero crossings will deviate from the ideal position by 0.1 unit intervals due to data jitter 108. As previously described, data jitter causes eye closure on both the left 106 and right 114 sides of the ideal digital pulse. A minimum eye opening 112 can be defined corresponding to a target BER. Thus, for a target BER, the total acceptable data jitter may be no greater than the sum of the left and right eye closures 106, 114 as shown. Accordingly, reducing tracking errors and BER is another primary consideration in designing CDR systems.
Therefore, in light of the foregoing description, it is desirable to develop novel and improved CDR systems with fast bit lock acquisition and small tracking error.